1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In general, it is desirable to have an integrated circuit fabrication process produce a semiconductor device with structures and spaces within certain dimension specifications. In some cases, the dimensions of structures and spaces within a device may be referred to as critical dimensions. “Critical dimension” (CD), as used in this application, may generally refer to the dimensional design value of a feature. Critical dimensions are of interest since they may represent the smallest dimension that may be formed on a semiconductor topography using various techniques such as photolithography and etch processes. In addition, it is desirable to have each processing step of a semiconductor fabrication process, including the photolithography and etch processes, produce a minimal amount of defects. Depending on a defect's size, location, and composition, a defect within a device may cause a failure within a subsequently formed integrated circuit. For example, a defect in a contact may increase resistance of the contact or may even prevent sufficient contact to the underlying structure. In other cases, defects may cause elevational disparities within a semiconductor topography, thereby making further deposition of layers and fabrication of structures difficult. Failures within integrated circuits can cause an increase in the overall manufacturing costs associated with integrated circuit fabrication.
As such, it is desirable for integrated circuit fabrication processes to be optimized such that the formation of defects is minimized and critical dimensions are well controlled. In order to reduce the amount of defects within an etch process, for example, and control the critical dimensions of a device component, different etch tools are typically used to etch different layers of a device structure. For example, oxide etch tools are generally used to etch dielectric materials and require high, energetic uniform ion bombardment such that defects may be minimized. In particular, oxide etch tools may produce a plasma density between approximately 2.0×1014 molecules/cm3 and approximately 2.0×1017 molecules/cm3 and may be referred to as “high-density” etch tools. In addition, oxide etch tools are typically run at a pressure between approximately 7.5 mTorr and 5.6 Torr. Generally, anti-reflective layers may be etched in an oxide etch tool since anti-reflective materials have similar properties of dielectric layers. Etching materials comprising silicon, however, typically requires higher CD control and thus requires low ion energies with precise wafer temperature control. As such, in an embodiment in which a topography including a dielectric and a material comprising silicon is etched, for example, the etch process may include using at least two different etch tools. In addition, the formation of defects within “silicon” etch tools, however, may be higher than in oxide etch tools. Consequently, an undesirable amount of defects may exist within a structure formed within a silicon etch tool.
It would, therefore, be desirable to develop an etch process that creates fewer defects during the fabrication of an integrated circuit. In particular, such an etch process preferably fabricates device components of the integrated circuit within critical dimension specifications.